Features:
- 12.5 Gb/s
- Bertscope
- Pattern generator
- Error analyzer
Specifications:
- Comprehensive range of differential divided clock outputs for supplying test devices with an instrument grade clock
- External clock input upgraded to allow imposition of stress
- Stressing of external Spread Spectrum Clock (SSC)
- Analysis (using clock recovery if desired) of signals with SSC
- Analysis of physical layer parameters such as eye diagrams and jitter while input signal has SCC on it
- BER measurements down to 100 Mb/s, operable with the internal clock or an external clock
- Variable depth eye and mask measurements
- Active measurement and graphing of BERTScope clock recovery loop bandwidth and peaking
- Jitter tolerance compliance template testing with margin testing
- Analyser with greater than 20 GHz bandwidth for superior jitter, Q-factor, and eye measurement accuracy and fidelity
The SyntheSys Research BSA12500B BERTScope has the features needed to perform receiver compliance testing, transmitter compliance testing, and advanced analysis. Featuring easy and flexible stress testing, physical layer analysis such as BER Contour and Jitter measurements, and a Compliance Contour view for Mask Test, it represents a breakthrough in insight and saved development time. Compliance Contour is a bridge between BER and mask testing, needed because of the requirements of standards such as OIF CEI and XFP/XFI. These new standards require compliance to masks at BER levels of 10-12, a feat beyond the capabilities of a sampling oscilloscope. BERTScope bridges the gap between eye diagram analysis with BER pattern generation. Finally, bit error ratio detection can be performed quickly, accurately, and thoroughly. BERTScope samples data and enables you to easily isolate problematic bit and pattern sequences. Seven types of advanced error analysis are built into one robust solution for unprecedented statistical measurement depth. For serial data applications, the new model BERTScopes provide great flexibility in clocking. This includes many new clock divide ratios, in addition to the ability to add stress to an external clock - even one with spread spectrum clocking imposed on it. Jitter tolerance testing is now a snap with onboard template testing. It all adds up to an even smarter way of getting your job done the fastest way possible.
The image is for reference only. See product specification for details.
| Manufacturer | Tektronix |
|---|---|
| Condition | Used |
| MAP | Error Mapping Analysis |
|---|---|
| PL | Physical Layer Test Suite: BER Contour |
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