Features:
- 17.5 Gb/s
- 100 MHz
- Integrated, calibrated stress generation to address the stressed receiver sensitivity and clock recovery jitter tolerance test requirements for a wide range of standards
- Electrical stressed eye testing
- Tolerance compliance template testing with margin testing
- Integrated eye diagram analysis with BER correlation
Applications:
- Design verification including signal integrity, jitter, and timing analysis
- Design characterization for high-speed, sophisticated designs
- Certification testing of serial data streams and high performance Networking systems
- Design/Verification of high-speed I/O components and systems
- Signal integrity analysis – mask testing, jitter peak, BER contour, jitter map, and q-factor analysis
- Design/Verification of optical transceivers
The Tektronix BSA175C is an analyzer.
Manufacturer | Tektronix |
---|---|
Condition | Used |
ECC | Add Error Correction Coding Emulation SW (included in STR) |
---|---|
F2 | F/2 Jitter Generation at 8G/10.3125G (requires STR) |
GSM | Generator Stress Module – Stressed Eye |
JTOL | Add Jitter Tolerance Templates SW (included in STR) |
MAP | Add Error Mapping Analysis SW (included in STR) |
PL | Add Physical Layer Test Suite SW (included in STR) |
SF | Add Symbol Filtering option SW (used with STR) |
SLD | Add Stressed Live Data option SW |
STR | Stressed Signal Generation (includes option ECC, MAP, PL, XSSC, JTOL) |
XSSC | Extended Spread Spectrum Clocking (SSC) (included in STR) |
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