P6230 Tektronix Active Probe

Used

Additional Features:

  • Bandwidth: DC to ≥ 1.5 GHz
  • Rise time: ≤ 230 ps
  • Attenuation: 10×
  • Input Impedance: 450 Ω // 1.3 pF (1.6 pF guaranteed)
  • Signal delay: 8.7 ± 0.1 ns
  • DC Offset range: -5 V ≤ (Vsignal + Voffset) ≤ +5 V
  • Readout Pin
  • Switchable 50 Ω termination

The Tektronix P6230 is a passive ×10 (450:50 Ω) probe with 1.5 GHz bandwidth and DC offset capability, intended to minimize DC probe-loading effect when used on logic circuits.

The P6230 has an offset control potentiometer in the termination box and connects to the scope, e.g. 7000 series scopes, through a BNC connector with ×10 readout pin. It can be powered from 7000 series mainframes having LEMO S-series connectors for probe power, or compatible units such as the 1101.

The P6230 shares accessories with many other Tektronix subminiature modular probes although the input hybrid is unique. Tip color is yellow, connector end color is blue, part number 206-0279-00. Its end to end resistance is 400 Ω.

The P6230 probe is sometimes described as FET probes or active probes, however, as the circuit diagram clearly shows, this is not correct. After the 400 Ω input hybrid, the AC component of the input signal is connected directly to the scope input through a 1 μF capacitor, then terminated in 50 Ω either in the scope input or the switchable terminator. The active circuit in the P623x, a standard NE5532 dual operational amplifer, has the function of restoring and offsetting the input signal's low-frequency and DC components. This approach is similar to the feed-beside technique used in the 7104 scope and 7A29 amplifier.

The P6230 acts as a standard 500 Ω passive voltage probe with the additional capability of having an adjustable tip "nulling voltage." This feature reduces the dc-loading effects on the probe when it is used to measure signals whose mid-voltage value is other than zero volts, or in circuits where the termination impedance is returned to other than ground level. The Input Bias/Offset Voltage may be adjusted so that at a particular test-signal voltage both ends of the probe input-resistor are at equal potentials and no current is flowing through the resistor.

ECL logic is most commonly operated from a -5.2 V supply with Vcc connected to ground. The output of an ECL gate is the emitter of an NPN emitter follower stage. The output is pulled down to a negative supply (about -2 V) with an external resistor (50 Ω to 100 Ω). Since speed is a major consideration in ECL designs, the interconnections between gates are often transmission lines, and the pull-down resistor doubles as a line termination.

If a standard 500 Ω, 10× probe without the input Bias/Offset feature were used to examine an ECL output, the probe's 500 Ω resistance to ground would form a voltage divider with the gate's output-termination resistor. This divider can cause distortion of the output signal levels, shift the DC operation point of the output transistor, and reduce the gate's noise margin.

The DC-load nulling capability of the P6230 helps to solve this problem. By adjusting the Input Bias/Offset Voltage to the ECL low level or to the termination voltage, the only effect of the probe resistance will be a small decrease in the ECL output-termination resistance. The effect of the probe on output voltage levels is negligible.

More Information
ManufacturerTektronix
ConditionUsed
Frequency1.5 GHz
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